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Deliang Fan

Asst Professor
Faculty, TEMPE Campus, Mailcode 5706
Biography: 

Deliang Fan is currently an assistant professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. Before joining ASU in 2019, he was an assistant professor in Department of Electrical and Computer Engineering at University of Central Florida, Orlando, Florida. He received his master's degree and doctoral degree under the supervision of Prof. Kaushik Roy, in electrical and computer engineering from Purdue University, West Lafayette, Indiana in 2012 and 2015, respectively.

For more details, please refer to https://dfan.engineering.asu.edu/

 

Research Interest:

  • Energy Efficient and High Performance Big Data Processing-In-Memory Circuit, Architecture and Algorithm, with applications in Deep Neural Network, Data Encryption, Graph Processing and Bioinformatics Processing-in-Memory system development
  • Efficient Deep Neural Network Accelerator Circuit and Architecture
  • Hardware Aware Deep Neural Network Compression and Optimization Algorithm
  • Security of Deep Neural Network Software and Hardware System
  • Brain-inspired (Neuromorphic) and Boolean Computing Using Emerging Nanoscale Devices like Spintronics, ReRAM and Memristors
  • Nano-scale Physics Based Spintronic Device (GMR/ TMR Vertical Spin Valve, Magnetic Skyrmion, Lateral Spin Valve, Magnetic Domain Wall Strip, Spin-Torque Oscillator, Spin-Orbit Torque ) Modeling and Simulations
  • Low Power Digital and Mixed Signal CMOS Circuit Design

 

Academic Awards:

  • Best Paper Award in 29th ACM Great Lakes Symposium on VLSI, Washington DC, USA, 2019
  • Best Paper Award in IEEE Computer Society Annual Symposium on VLSI, Hong Kong, China, 2018
  • Best Paper Award in IEEE Computer Society Annual Symposium on VLSI, Bochum, Germany, 2017
  • Best Paper Candidate in Asia and South Pacific Design Automation Conference, Tokyo, Japan, 2019
  • Front Cover Paper in IEEE Transactions on Magnetics, Vol. 54, No.2, Feb. 2018
  • Schloss Dagstuhl - NSF Support for Junior Researchers, 2019

 

Academic Activities and Services:

Dr. Fan has authored and co-authored 100+ peer-reviewed international journal/conference papers. His research group is funded by National Science Foundation (NSF), Semiconductor Research Corporation (SRC), Cyber Florida, SCEEE Research Initiation grant, NanoScience Technology Center at UCF seed grant and UCF InHouse grant, etc. He served as technical reviewers for over 30 international journals/conferences, such as Nature Electronics, IEEE TNNLS, TVLSI, TCAD, TNANO, TC, TCAS, ISCAS, ISLPED, etc. He also served as the Technical Program Committee member of DAC, ICCAD, GLSVLSI, ISVLSI, ASP-DAC, ISQED, etc. He is also the technical area chair of GLSVLSI 2019, ISQED 2019/2020, and the financial chair of ISVLSI 2019.

Education: 
  • Ph.D. Electrical and Computer Engineering,  Purdue University ,  West Lafayette, IN 2015
  • M.S. Electrical and Computer Engineering, Purdue University,  West Lafayette, IN 2012 
  • Bachelor's degree. Electronic Information Engineering, Zhejiang University, Hangzhou, China 2010
Publications: 

JOURNAL PUBLICATIONS

  1. [TNNLS'20] Xiaolong Ma, Sheng Lin, Shaokai Ye, Zhezhi He, Linfeng Zhang, Geng Yuan, Sia Huat Tan, Zhenggang Li, Deliang Fan, Xuehai Qian, Xue Lin, Kaisheng Ma, and Yanzhi Wang, “Non-Structured DNN Weight Pruning – Is It Beneficial in Any Platform?,” IEEE Transactions on Neural Networks and Learning Systems (TNNLS), 2020 (conditional accept)
  2. [EDL'20] Durjoy Dev, Adithi Krishnaprasad, Mashiyat S. Shawkat, Zhezhi He, Sonali Das, Deliang Fan, Hee-Suk Chung, Yeonwoong Jung, and Tania Roy, “2D MoS2 Based Threshold Switching Memristor For Artificial Neuron,” IEEE Electron Device Letters (EDL), 2020 (accept)
  3. [TMAG'20] Shaahin Angizi, Zhezhi He, An Chen and Deliang Fan, “Hybrid Spin-CMOS Polymorphic Logic Gate with Application in In-Memory Computing,” IEEE Transactions on Magnetics (TMAG) , Volume: 56 , Issue: 2 , Feb. 2020, DOI: 10.1109/TMAG.2019.2955626 [pdf]
  4. [JETC'20] Zhezhi He, Li Yang, Shaahin Angizi, Adnan Siraj Rakin and Deliang Fan, “Sparse BD-Net: A Multiplication-Less DNN with Sparse Binarized Depth-wise Separable Convolution,” ACM Journal on Emerging Technologies in Computing Systems (JETC), January 2020 Article No.: 15 https://doi.org/10.1145/3369391 [pdf]
  5. [Bioinformatics'19] Zhibo Wang, Zhezhi He, Milan Shah, Teng Zhang, Deliang Fan and Wei Zhang, “Network-based multi-task learning models for biomarker selection and cancer outcome prediction,” Bioinformatics, btz809, https://doi.org/10.1093/bioinformatics/btz8092019, 05 November 2019 [pdf]
  6. [TC'19] Arman Roohi, Shadi Sheikhfaal, Shaahin Angizi, Deliang Fan, Ronald DeMara, “ApGAN: Approximate GAN for Robust Low Energy Learning from Imprecise Components,” IEEE Transactions on Computers, 23 October 2019, DOI: 10.1109/TC.2019.2949042 [pdf]
  7. [TCAD'19] Baogang Zhang, Necati Uysal, Deliang Fan, Rickard Ewetz, “Handling Stuck-at-fault Defects using Matrix Transformation for Robust Inference of DNNs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 30 September 2019, DOI: 10.1109/TCAD.2019.2944582  [pdf]
  8. [TCAD'19] Shaahin Angizi, Zhezhi He, Amro Awad and Deliang Fan, “MRIMA: An MRAM-based In-Memory Accelerator,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27 March 2019, DOI: 10.1109/TCAD.2019.2907886  [pdf]
  9. [JETC'18] Farhana Parveen, Shaahin Angizi and Deliang Fan, “IMFlexCom: Energy Efficient In-memory Flexible Computing using Dual-mode SOT-MRAM,” ACM Journal on Emgerging Technologies in Computing Systems, Vol.14, no.3, Oct. 2018 [pdf]
  10. [TNANO'18] Shaahin Angizi, Honglan Jiang, Ronald Demara, Jie Han and Deliang Fan, “Majority-Based Spin-CMOS Primitives for Approximate Computing,” IEEE Transactions on Nanotechnology, vol. 17, no. 4, July 2018 [pdf]
  11. [TMSCS'18] Zhezhi He, Yang Zhang, Shaahin Angizi, Boqing Gong and Deliang Fan, “Exploring A SOT-MRAM based In-Memory Computing for Data Processing,” IEEE Transactions on Multi-Scale Computing Systems, 2018 [pdf]
  12. [TMAG'18] Farhana Parveen, Shaahin Angizi, Zhezhi He and Deliang Fan, “IMCS2: Novel Device-to-Architecture Co-design for Low Power In-memory Computing Platform using Coterminous Spin-Switch,” IEEE Transactions on Magnetics, vol. 54, no.7, July 2018 [pdf]
  13. [TMAG'18] S. Pyle, D. Fan, R. DeMara, “Compact Spintronic Muller C-Element with Near-Zero Standby Energy,” IEEE Transactions on Magnetics, vol.54, no.2, Feb. 2018 [pdf] (Front Cover Paper)
  14. [TMSCS'17] Y. Bai, D. Fan and M. Lin, “Stochastic-Based Synapse and Soft-Limiting Neuron with Spintronic Devices for Low Power and Robust Artificial Neural Networks,” IEEE Transactions on Transactions on Multi-Scale Computing Systems, vol.4, no.3, pp.463-476, Dec. 2017 [pdf]
  15. [TCAD'17] S. Angizi, Z. He, N. Bagherzadeh and D. Fan, “Design and Evaluation of a Spintronic In-Memory Processing Platform for Non-Volatile Data Encryption,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.37, no.9, Sept. 2018 [pdf]
  16. [MAGL'17] Z. He, S. Angizi, and D. Fan, “Current Induced Dynamics of Multiple Skyrmions with Domain Wall Pair and Skyrmion-based Majority gate Design,” IEEE Magnetics Letters, vol.8, March 30, 2017 [pdf]
  17. [TCAD'17] A. Roohi, R. Zand, D. Fan and R. DeMara, “Voltage-based Concatenatable Full Adder using Spin Hall Effect Switching,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol.36, no.12, Dec. 2017 [pdf]
  18. [JETC'17] K. Yogendra, C. Liyanagedera, D. Fan, Y. Shim and K. Roy, “Coupled Spin-Torque Nano-Oscillator based Computation: A Simulation Study,” ACM Journal on Emerging Technologies in Computing Systems, vol. 13, no.4, July 2017 [pdf]
  19. [TETC'17] Z. He and D. Fan, “Energy Efficient Reconfigurable Threshold Logic Circuit with Spintronic Devices,” IEEE Transactions on Emerging Topics in Computing, vol.5, no.2, May 2017 [pdf]
  20. [JETCAS'17] S. Salehi, D. Fan, R. DeMara, “Survey of STT-MRAM Cell Design Strategies: Taxonomy and Sense Amplifier Tradeoffs for Resiliency,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 13, no. 3, May 2017 [pdf]
  21. [TNANO'17] R. Zand, A. Roohi, D. Fan and R. DeMara, “Energy-Efficient Nonvolatile Reconfigurable Logic using Spin Hall Effect-based Lookup Tables,” IEEE Transactions on Nanotechnology, vol. 16, no. 1, pp.32-43, Jan. 2017 [pdf]
  22. [TCAD'16] X. Fong, Y. Kim, K. Yogendra, D. Fan, A. Sengupta, and K. Roy, “Spin-Transfer Torque Devices: Prospects and Perspectives,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, no. 1, pp.1-22, Jan 2016, [pdf]
  23. [TED'16] K Yogendra, D. Fan, B. Jung and K. Roy, “Magnetic Pattern Recognition using Injection Locked Spin Torque Nano-Oscillators", IEEE Transactions on Electron Devices, vol. 63, no. 4, pp.1674-1680, Feb. 2016 [pdf]
  24. [TNANO'15] D. Fan, S. Maji, K. Yogendra, M. Sharad and K. Roy, “Injection Locked, Spin Hall Induced Coupled-Oscillators for Energy Efficient Associative Computing,” IEEE Transaction on Nanotechnology (TNANO), Vol. 14, No. 6, Aug, 2015. DOI: 10.1109/TNANO.2015.2471092 [pdf]
  25. [TNNLS'15] D. Fan, M. Sharad, A. Sengupta and K. Roy, “Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing,” IEEE Transaction on Neural Networks and Learning Systems (TNNLS), Vol.27, no.9, Sept. 2016. DOI: 10.1109/TNNLS.2015.2462731 [pdf]
  26. [TNANO'15] D. Fan, Y. Shim, A. Raghunathan and K. Roy, “STT-SNN: A Spin-Transfer-Torque Based Non-Linear Soft-Limiting Neuron for Low-Power Artificial Neural Networks,” IEEE Transactions on Nanotechnology (TNANO), June 2015. DOI: 10.1109/TNANO.2015.2437902 [pdf]
  27. [TMAG'15] K Yogendra, D. Fan and K. Roy, “Coupled Spin Torque Nano Oscillators for Low Power Neural Computation”, IEEE Transactions on Magnetics, Vol. 51, no. 10, June, 2015. DOI: 10.1109/TMAG.2015.2443042 [pdf]
  28. [TMAG'15] M. Sharad, D. Fan and K. Roy, “Energy-Efficient and Robust Associative Computing with Injection-Locked Dual Pillar Spin-Torque Oscillators”, IEEE Transactions on Magnetics, Vol. 51, No. 7, June 2015. DOI: 10.1109/TMAG.2015.2394379 [pdf]
  29. [JETCAS'15] K. Roy, D. Fan, X. Fong, Y. Kim, M. Sharad, S. Paul, S. Chatterjee, S. Bhunia, and S. Mukhopadhyay “Exploring Spin Transfer Torque Devices for Unconventional Computing”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), Vol. 5, No. 1, March 2015. DOI: 10.1109/JETCAS.2015.2405171 [pdf]
  30. [TNANO'14] D. Fan, M. Sharad and K. Roy, “Design and Synthesis of Ultra Low Energy Spin-Memristor Threshold Logic,” IEEE Transaction on Nanotechnology (TNANO) Vol. 13, No. 3, May, 2014. DOI: 10.1109/TNANO.2014.2312177 [pdf]
  31. [TNANO'14] M. Sharad, D. Fan, and K. Roy, “Energy Efficient Non-Boolean Computing With Spin Neurons and Resistive Memory”, IEEE Transaction on Nanotechnology (TNANO), vol. 13, No.1, 2014. DOI: 10.1109/TNANO.2013.2286424 [pdf]
  32. [JAP'13] M. Sharad, D. Fan and K. Roy , “Spin Neurons: A Possible Path to Energy-Efficient Neuromorphic Computers”, Journal of Applied Physics (JAP), 114, 234906 (2013) http://dx.doi.org/10.1063/1.4838096 [pdf]



CONFERENCE PUBLICATIONS

  1. [USENIX Security’20]  Fan Yao, Adnan Siraj Rakin and Deliang Fan, “DeepHammer: Depleting the Intelligence of Deep Neural Networks through Targeted Chain of Bit Flips,” In 29th USENIX Security Symposium (USENIX Security 20), August 12-14, 2020, Boston, MA, USA [pdf]  
  2. [ISLPED’20] Mingyen Lee, Wenjun Tang, Bowen Xue, Juejian Wu, Mingyuan Ma, Yu Wang, Yongpan Liu, Deliang Fan, Vijaykrishnan Narayanan, Huazhong Yang and Xueqing Li, “FeFET-Based Low-Power Bitwise Logic-in-Memory with Direct Write-Back and Data-Adaptive Dynamic Sensing Interface”, ACM/IEEE International Symposium on Low Power Electronics and Design, August 10-12, 2020
  3. [GLSVLSI’20] Shaahin Angizi, Wei Zhang and Deliang Fan, “Exploring DNA Alignment-in-Memory Leveraging EmergingSOT-MRAM”, 30th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI), September 7-9, 2020 (invited)
  4. [GLSVLSI’20] Adnan Siraj Rakin, Zhezhi He, Li Yang, Yanzhi Wang, Liqiang Wang, Deliang Fan, “Robust Sparse Regularization: Simultaneously Optimizing Neural Network Robustness and Compactness”, 30th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI), September 7-9, 2020 (invited)
  5. [GLSVLSI’20] Dayane Reis, Di Gao, Shaahin Angizi, Xunzhao Yin, Deliang Fan, Michael Niemier, Cheng Zhuo and X. Sharon Hu, “Exploring DNA Alignment-in-Memory Leveraging EmergingSOT-MRAM”, 30th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI), September 7-9, 2020 (invited)
  6. [CVPR'20]  Adnan Siraj Rakin, Zhezhi He and Deliang Fan, “TBT: Targeted Neural Network Attack with Bit Trojan,” 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), June 16-18, 2020, Seattle, Washington, USA 
  7. [CVPR'20]  Zhezhi He,Adnan Siraj Rakin, Jingtao Li, Chaitali Chakrabarti and Deliang Fan, “Defending and Harnessing the Bit-Flip based Adversarial Weight Attack,” 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), June 16-18, 2020, Seattle, Washington, USA 
  8. [DAC’20] Li Yang, Zhezhi He, Yu Cao and Deliang Fan. “Non-uniform DNN Structured Subnets Sampling for Dynamic Inference”. In: 57th Design Automation Conference (DAC), San Francisco, CA, July 19-23, 2020 (Accepted).
  9. [DAC’20] Shaahin Angizi, Naima Ahmed Fahmi, Wei Zhang and Deliang Fan, “PIM-Assembler: A Processing-in-Memory Platform for Genome Assembly” In: 57th Design Automation Conference (DAC), San Francisco, CA, July 19-23, 2020 (Accepted).
  10. [DAC’20] Jingtao Li, Adnan Siraj Rakin, Yan Xiong, Liangliang Chang, Zhezhi He, Deliang Fan, and Chaitali Chakrabarti. “Defending Bit-Flip Attack through DNN Weight Reconstruction”. In: 57th Design Automation Conference (DAC), San Francisco, CA, July 19-23, 2020. (Accepted).
  11. [AAAI'20] Li Yang, Zhezhi He and Deliang Fan, “Harmonious Coexistence of Structured Weight Pruning and Ternarization for Deep Neural Networks,” Thirty-Fourth AAAI Conference on Artificial Intelligence (AAAI), Feb. 7-12 2020, New York, USA (spotlight)
  12. [DATE'20] Shaahin Angizi, Jiao Sun, Wei Zhang and Deliang Fan, “PIM-Aligner: A Processing-in-MRAM Platform for Biological Sequence Alignment,” Design, Automation and Test in Europe (DATE), 09-13 March 2020, ALPEXPO, Grenoble, France
  13. [ASPDAC'20] Li Yang, Shaahin Angizi, Deliang Fan, “A Flexible Processing-in-Memory Accelerator for Dynamic Channel-Adaptive Deep Neural Networks,” Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 13-16, 2020, Beijing, China 
  14. [ASPDAC'20] Baogang Zhang, Necati Uysal, Deliang Fan, Rickard Ewetz, “Representable Matrices: Enabling High Accuracy Analog Computation for Inference of DNNs using Memristors,” Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 13-16, 2020, Beijing, China 
  15. [ICCV'19] Adnan Siraj Rakin* , Zhezhi He*, Deliang Fan, “Bit-Flip Attack: Crushing Neural Network with Progressive Bit Search,” IEEE International Conference on Computer Vision, Seoul, Korea, Oct 27 - Nov 3, 2019 [pdf] (* The first two authors contributed equally)
  16. [ICCAD'19] Shaahin Angizi and Deliang Fan, “ReDRAM: A Reconfigurable Processing-in-DRAM Platform for Accelerating Bulk Bit-Wise Operations,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 4-7 November 2019, Westminster, CO [pdf]
  17. [NANOARCH'19] Shaahin Angizi and Deliang Fan, “Deep Neural Network Acceleration in Non-Volatile Memory: A Digital Approach?,” IEEE/ACM International Symposium on Nanoscale Architectures, 17-19 July 2019, Qingdao, CHINA
  18. [ISVLSI'19] Shaahin Angizi, Zhezhi He, Dayane Reis, Xiaobo Sharon Hu, Wilman Tsai, Shy Jay Lin and Deliang Fan, “Accelerating Deep Neural Networks in Processing-in-Memory Platforms: Analog or Digital Approach?,” IEEE Computer Society Annual Symposium on VLSI, 15 - 17 July 2019, Miami, Florida, USA (invited)
  19. [ISVLSI'19] Adnan Siraj Rakin and Deliang Fan, “Defense-Net: Defend Against a Wide Range of Adversarial Attacks through Adversarial Detector,” IEEE Computer Society Annual Symposium on VLSI, 15 - 17 July 2019, Miami, Florida, USA
  20. [Dagstuhl Report’19] Deliang Fan, “Cognitive Computing-in-Memory: Circuit to Algorithm,” Dagstuhl Seminar 19152, Emerging Hardware Techniques and EDA Methodologies for Neuromorphic Computing, Germany, 2019
  21. [DRC'19] Durjoy Dev, Adithi Krishnaprasad, Zhezhi He, Sonali Das, Mashiyat Sumaiya Shawkat, Madison Manley, Olaleye Aina, Deliang Fan, Yeonwoong Jung and Tania Roy, “Artificial Neuron using Ag/2D-MoS2/Au Threshold Switching Memristor,” 77th Device Research Conference, 23 - 26 June 2019, University of Michigan, Ann Arbor
  22. [CVOPS'19] Yifan Ding, Liqiang Wang, Huan Zhang, Jinfeng Yi, Deliang Fan, and Boqing Gong, “Defending Against Adversarial Attacks Using Random Forests,” Workshop on The Bright and Dark Sides of Computer Vision: Challenges and Opportunities for Privacy and Security, June 16-20, 2019, Long Beach, CA, USA [pdf]
  23. [CVPR'19] Zhezhi He*, Adnan Siraj Rakin* and Deliang Fan, “Parametric Noise Injection: Trainable Randomness to Improve Deep Neural Network Robustness against Adversarial Attack,” Conference on Computer Vision and Pattern Recognition (CVPR), June 16-20, 2019, Long Beach, CA, USA (* The first two authors contributed equally) [pdf] [code in GitHub]
  24. [CVPR'19] Zhezhi He and Deliang Fan, “Simultaneously Optimizing Weight and Quantizer of Ternary Neural Network using Truncated Gaussian Approximation,” Conference on Computer Vision and Pattern Recognition (CVPR), June 16-20, 2019, Long Beach, CA, USA [pdf]
  25. [GLSVLSI'19] Shaahin Angizi and Deliang Fan, “GraphiDe: A Graph Processing Accelerator leveraging In-DRAM-Computing,” ACM Great Lakes Symposium on VLSI(GLSVLSI), May 9-11, 2019, Washington, D.C. USA ( Best Paper Award[pdf]
  26. [GLSVLSI'19] Li Yang, Zhezhi He and Deliang Fan, “Binarized Depthwise Separable Neural Network for Object Tracking in FPGA,” ACM Great Lakes Symposium on VLSI(GLSVLSI), May 9-11, 2019, Washington, D.C. USA [pdf]
  27. [DAC'19] Shaahin Angizi, Jiao Sun, Wei Zhang and Deliang Fan, “AlignS: A Processing-In-Memory Accelerator for DNA Short Read Alignment Leveraging SOT-MRAM,” Design Automation Conference (DAC), June 2-6, 2019, Las Vegas, NV, USA [pdf]
  28. [DAC'19] Zhezhi He, Jie Lin, Rickard Ewetz, Jiann-Shiun Yuan and Deliang Fan, “Noise Injection Adaption: End-to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping,” Design Automation Conference (DAC), June 2-6, 2019, Las Vegas, NV, USA [pdf] [code in GitHub]
  29. [ISQED'19] Arman Roohi, Shaahin Angizi, Deliang Fan and Ronald F DeMara, “Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Efficiency and Power-Intermittency Resilience,” The 20th International Symposium on Quality Electronic Design (ISQED), March 6-7, 2019, Santa Clara, CA, USA
  30. [DATE'19] Shaahin Angizi, Jiao Sun, Wei Zhang and Deliang Fan, “GraphS: A Graph Processing Accelerator Leveraging SOT-MRAM,” Design, Automation and Test in Europe (DATE), March 25-29, 2019, Florence, Italy. [pdf]
  31. [WACV'19] Zhezhi He, Boqing Gong, Deliang Fan, “Optimize Deep Convolutional Neural Network with Ternarized Weights and High Accuracy,” IEEE Winter Conference on Applications of Computer Vision, January 7-11, 2019, Hawaii, USA [pdf][code in GitHub]
  32. [ASPDAC'19] Shaahin Angizi, Zhezhi He and Deliang Fan, “ParaPIM: A Parallel Processing-in-Memory Accelerator for Binary-Weight Deep Neural Networks,” Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 21-24, 2019, Tokyo, Japan [pdf]
  33. [ASPDAC'19] Baogang Zhang, Necati Uysal, Deliang Fan, Rickard Ewetz, “Handling Stuck-at-faults in Memristor Crossbar Arrays using Matrix Transformations,” Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 21-24, 2019, Tokyo, Japan [pdf]( Best Paper Candidate)
  34. [ICCD'18] Adnan Siraj Rakin, Shaahin Angizi, Zhezhi He and Deliang Fan, “PIM-TGAN: A Processing-in-Memory Accelerator for Ternary Generative Adversarial Networks,” IEEE International Conference on Computer Design (ICCD) , Oct. 7-10, 2018, Orlando, FL, USA [pdf]
  35. [ICCAD'18] Shaahin Angizi, Zhezhi He and Deliang Fan, “DIMA: A Depthwise CNN In-Memory Accelerator,” IEEE/ACM International Conference on Computer Aided Design, Nov. 5-8, 2018, San Diego, CA, USA [pdf]
  36. [ISLPED'18] Li Yang, Zhezhi He and Deliang Fan, “A Fully Onchip Binarized Convolutional Neural Network FPGA Implementation with Accurate Inference,” ACM/IEEE International Symposium on Low Power Electronics and Design, July 23-25, 2018, Bellevue, Washington, USA [pdf]
  37. [ISVLSI'18] Zhezhi He, Shaahin Angizi, Adnan Siraj Rakin and Deliang Fan, “BD-NET: A Multiplication-less DNN with Binarized Depthwise Separable Convolution,” IEEE Computer Society Annual Symposium on VLSI, July 9-11, 2018, Hong Kong, CHINA [pdf] ( Best Paper Award )
  38. [ISVLSI'18] Zhezhi He, Shaahin Angizi and Deliang Fan, “Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM,” IEEE Computer Society Annual Symposium on VLSI, July 9-11, 2018, Hong Kong, CHINA (invited) [pdf]
  39. [GLSVLSI'18] Shaahin Angizi, Zhezhi He, Yu Bai, Jie Han, Mingjie Lin and Deliang Fan, “Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Network,” ACM Great Lakes Symposium on VLSI (GLSVLSI), Chicago, IL, USA, May 23-25, 2018 (invited) [pdf]
  40. [DAC'18] Shaahin Angizi*, Zhezhi He*, Adnan Siraj Rakin and Deliang Fan, “CMP-PIM: An Energy-Efficient Comparator-based Processing-In-Memory Neural Network Accelerator,” IEEE/ACM Design Automation Conference (DAC), June 24-28, 2018, San Francisco, CA, USA (* The first two authors contributed equally) [pdf]
  41. [DAC'18] Shaahin Angizi, Zhezhi He and Deliang Fan, “PIMA-Logic: A Novel Processing-in-Memory Architecture for Highly Flexible and Energy-Efficient Logic Computation, ” IEEE/ACM Design Automation Conference (DAC), June 24-28, 2018, San Francisco, CA, USA [pdf]
  42. [WACV'18] Y. Ding, L. Wang, D. Fan and B. Gong “A Semi-Supervised Two-Stage Approach to Learning from Noisy Labels,” IEEE Winter Conference on Applications of Computer Vision, March 12-14, 2018, Stateline, NV, USA [pdf]
  43. [ASPDAC'18] F. Parveen, Z. He, S. Angizi and D. Fan, “HieIM: Highly Flexible In-Memory Computing using STT MRAM,” Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 22-25, 2018, Jeju Island, Korea [pdf]
  44. [ASPDAC'18] S. Angizi, Z. He, F. Parveen and D. Fan, “IMCE: Energy-Efficient Bit-Wise In-Memory Convolution Engine for Deep Neural Network,” Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 22-25, 2018, Jeju Island, Korea [pdf]
  45. [ICCD'17] Z. He, S. Angizi and D. Fan, “Exploring STT-MRAM based In-Memory Computing Paradigm with Application of Image Edge Extraction,” IEEE International Conference on Computer Design (ICCD) , Nov. 5-8, 2017, Boston, MA [pdf]
  46. [ICCD'17] D. Fan and S. Angizi “Energy Efficient In-Memory Binary Deep Neural Network Accelerator with Dual-Mode SOT-MRAM,” IEEE International Conference on Computer Design (ICCD) , Nov. 5-8, 2017, Boston, MA [pdf]
  47. [NCAMA'17] S. Angizi and D. Fan , “IMC: Energy-Efficient In-Memory Convolver for Accelerating Binarized Deep Neural Network,” Neuromorphic Computing Symposium: Architectures, Models, and Applications , July 17-19, 2017, Knoxville, Tennessee [pdf]
  48. [ICCAD'17] M. Yang, J. Hayes, D. Fan and W. Qian, “Design of Accurate Stochastic Number Generators with Noisy Emerging Devices for Stochastic Computing,” IEEE/ACM International Conference on Computer Aided Design, Nov 13-16, Irvin, CA [pdf]
  49. [ISLPED'17] F. Parveen, S. Angizi, Z. He and D. Fan , “Low Power In-Memory Computing based on Dual-Mode SOT-MRAM,” IEEE/ACM International Symposium on Low Power Electronics and Design, July 24-26, 2017, Taipei, Taiwan [pdf]
  50. [NANOARCH'17] Z. He, S. Angizi, F. Parveen and D. Fan , “High Performance and Energy-Efficient In-Memory Computing Architecture based on SOT-MRAM,” IEEE/ACM International Symposium on Nanoscale Architectures , July 25-26, 2017, Newport, USA [pdf]
  51. [ISVLSI'17] D. Fan, S. Angizi and Z. He, “In-Memory Computing with Spintronic Devices,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 3-5, 2017, Bochum, Germany (invited) [pdf]
  52. [ISVLSI'17] S. Angizi, Z. He, F. Parveen and D. Fan, “RIMPA: A New Reconfigurable Dual-Mode In-Memory Processing Architecture with Spin Hall Effect-Driven Domain Wall Motion Device,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 3-5, 2017, Bochum, Germany [pdf]
  53. [ISVLSI'17] F. Parveen, Z. He, S. Angizi and D. Fan, “Hybrid Polymorphic Logic Gate with 5-Terminal Magnetic Domain Wall Motion Device,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 3-5, 2017, Bochum, Germany [pdf] ( Best Paper Award )
  54. [MWSCAS'17] D. Fan, Z. He and S. Angizi, “Leveraging Spintronic Devices for Ultra-Low Power In-Memory Computing: Logic and Neural Network,” 60th IEEE International Midwest Symposium on Circuits and Systems, Aug. 6-9, 2017, Boston, MA, USA (invited) [pdf]
  55. [ISCAS'17] F. Parveen, S. Angizi, Z. He and D. Fan, “Hybrid Polymorphic Logic Gate Using 6 Terminal Magnetic Domain Wall Motion Device,” IEEE International Symposium on Circuits & Systems (ISCAS), Baltimore, MD, USA, May 28-31, 2017 [pdf]
  56. [GLSVLSI'17] Z. He, S. Angizi, F. Parveen, and D. Fan, “Leveraging Dual-Mode Magnetic Crossbar for Ultra-low Energy In-Memory Data Encryption”, 27th GLSVLSI, Banff, Alberta, Canada, May 10-12, 2017 [pdf]
  57. [GLSVLSI'17] S. Angizi, Z. He, and D. Fan, “Energy Efficient In-Memory Computing Platform Based on 4-Terminal Spin Hall Effect-Driven Domain Wall Motion Devices”, 27th GLSVLSI, Banff, Alberta, Canada, May 10-12, 2017 [pdf]
  58. [GLSVLSI'17] Q. Alasad, J. Yuan, and D. Fan, “Leveraging All-Spin Logic to Improve Hardware Security”, 27th GLSVLSI, Banff, Alberta, Canada, May 10-12, 2017 [pdf]
  59. [DATE'17] Z. He, D. Fan, “A Tunable Magnetic Skyrmion Neuron Cluster for Energy Efficient Artificial Neural Network,” Design, Automation and Test in Europe (DATE), Lausanne, Switzerland, 27-31 March, 2017 [pdf]
  60. [ISQED'17] S. Angizi, Z. He, R. DeMara and D. Fan, “Composite Spintronic Accuracy-Configurable Adder for Low Power Digital Signal Processing,” 18th International Symposium on Quality Electronic Design(ISQED), Santa Clara, CA, USA, 13-15 March, 2017[pdf]
  61. [ISLPED'16] Z. He and D. Fan, “A Low Power Current-Mode Flash ADC with Spin Hall Effect based Multi-Threshold Comparator”, International Symposium on Low Power Electronics and Design (ISLPED), San Francisco, CA, Aug. 8-10, 2016[pdf]
  62. [NANOARCH'16] D. Fan, “Low Power In-Memory Computing Platform with Four Terminal Magnetic Domain Wall Motion Devices”, IEEE/ ACM International Symposium on Nanoscale Architectures, , Beijing, China, July 18-20, 2016 [pdf]
  63. [GLSVLSI'16] D. Fan, “ Ultra-Low Energy Reconfigurable Spintronic Threshold Logic Gate”, 26th GLSVLSI, Boston, Massachusetts, May 18-20, 2016[pdf]
  64. [IJCNN'16] C. Liyanagedera, K. Yogendra, K. Roy and D. Fan, “ Spin Torque Nano-Oscillator based Oscillatory Neural Network”, 2016 IEEE International Joint Conference on Neural Network (IJCNN), Vancouver, Canada, July 24-29, 2016[pdf]
  65. [ASPDAC'16] K. Yogendra, D. Fan, Y. Shim, M. Koo, and K. Roy, “ Computing with Coupled Spin Torque Nano Oscillators”, 21st Asia and South Pacific Design Automation Conference (ASP-DAC), Macao, China, Jan. 25-28, 2016[pdf]
  66. [ASPDAC'16] A. Sengupta, K. Yogendra, D. Fan and K. Roy, “Prospects of efficient neural computing with arrays of magneto-metallic neurons and synapses”, 21st Asia and South Pacific Design Automation Conference (ASP-DAC), Macao, China, Jan. 25-28, 2016[pdf]
  67. [DATE'14] K. Roy, M. Sharad, D. Fan and K. Yogendra, “Brain-inspired computing with spin torque devices”, Design, Automation & Test in Europe (DATE), 2014. (invited tutorial)[pdf]
  68. [ISVLSI'14] K. Roy, M. Sharad, D. Fan and K. Yogendra, “Computing with Spin-Transfer-Torque Devices: Prospects and Perspectives,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, FL, July 9-11, 2014 (special session paper)[pdf]
  69. [DAC'13] M. Sharad, D. Fan, and K. Roy, “Ultra Low Power Associative Computing With Spin Neurons and Resistive Crossbar Memory,” IEEE/ACM Design Automation Conference (DAC), Austin, TX, June 2-6, 2013[pdf]
  70. [ISLPED'13] K. Roy, M. Sharad, D. Fan, and K. Yogendra, “Beyond Charge-Base Computing: Boolean and Non Boolean computing Using spin Devices,” International Symposium on Low Power and Design (ISLPED), 2013. (invited tutorial)[pdf]
  71. [ICCAD'13] K. Roy, M. Sharad, D. Fan, and K. Yogendra, “Exploring Boolean and Non Boolean Computing Using Spin torque Switches” International Conference on Computer-Aided Design (ICCAD), 2013. (invited tutorial)[pdf]
  72. [ISQED'13] M. Sharad, D. Fan, and K. Roy, “Low Power and Compact Mixed-Mode Signal Processing Hardware using Spin-Neurons,” IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, March 4-6, 2013[pdf]
  73. [E3S'13] M. Sharad, D. Fan, K. Yogendra, and K. Roy, “Ultra-Low Power Neuromorphic Computing with Spin-Torque Devices,” 3rd Berkeley Symposium on Energy Efficient Electronic Systems, 2013[pdf]
Research Activity: 
  • National Science Foundation (NSF): FET: Small: “AlignMEM: Fast and Efficient DNA Sequence Alignment in Non-Volatile Magnetic RAM”, 2019-2022; Role: Leading-PI, $491,298; NSF Award number: 1908495
  • National Science Foundation (NSF): CPS: Medium: “A Secure, Trustworthy, and Reliable Air Quality Monitoring System for Smart and Connected Communities”, 2019-2022; Role: PI of ASU, $1,198,111; NSF award number: 1931871
  • National Science Foundation (NSF): E2CDA: “Non-Volatile In-Memory Processing Unit: Memory, In-Memory Logic and Deep Neural Network” 2017-2020; Role: Sole-PI, $184,470; NSF award number: 1740126
  • Semiconductor Research Corporation (SRC): E2CDA: “Non-Volatile In-Memory Processing Unit: Memory, In-Memory Logic and Deep Neural Network” 2017-2020, Role: Sole-PI, $92,235
  • H Lee Moffitt Cancer Center and Research Institute, Inc.: Development of a mathematically-based clinical decision support tool for multiple myeloma,”, 2020 – 2021; Role: PI of ASU; $150,000 
  • Cyber Florida: “Towards Robust Deep Learning Systems Against Adversarial Attacks,” 2019-2020, $75,000; Role: Leading-PI
  • UCF NanoScience Technology Center (NSTC) Research Seed Award, “3D nanotubular metal-insulator-metal memristors for neuro-inspired artificial intelligence”, 2019, Role: Co-PI, $30,000
  • Southeastern Center for Electrical Engineering Education (SCEEE), Research Initiation Grant, “Ultra-Low Energy Brain-Inspired Computing using Nanoscale Emerging Spintronic Devices,” 2016-2017, Role: Sole-PI, $44,00 ($22,000 + $22,000 UCF matching fund)
  • UCF In-House Award, “Self-Sustained Spin-Transfer Torque Devices based Brain-inspired Processor Powered by Energy Harvesting Technology for Internet of Things Applications,” 2016-2017; Role: Sole-PI, $7,500
Presentations: 

Courses at Arizona State University

Fall 2019: instructor of EEE 425 Digital Systems and Circuits

Course Objective: To be able to analyze and design digital integrated circuits.
Course Description: Digital logic gate analysis and design. Propagation delay times, fan out, power dissipation, noise margins. Design and analysis of CMOS circuits - combinational and sequential logic circuits. MOS memories. VLSI circuits. Cadence for circuit layout and simulation.

 

Editorships: 

 

Technical Program Committee of International Conference

  • Design Automation Conference (DAC) 2018/2019/2020
  • International Conference on Computer Aided Design (ICCAD) 2018/2019/2020
  • IEEE International Symposium on High-Performance Computer Architecture (HPCA) 2020
  • IEEE/ACM International Symposium on Microarchitecture (Micro) 2020
  • Design, Automation and Test in Europe (DATE) 2020
  • ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) 2020
  • Asia and South Pacific Design Automation Conference (ASP-DAC) 2018/2019/2020
  • Design Automation Conference (DAC) Late Breaking Results 2020
  • Great Lakes Symposium on VLSI (GLSVLSI) 2017/2018/2019
  • IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2017/2018/2019
  • IEEE International Symposium on Circuits and Systems (ISCAS) 2019
  • International Conference on VLSI Design 2020
  • The 20th International Symposium on Quality Electronic Design (ISQED) 2019
  • SIGDA PhD Forum at Design Automation Conference (DAC) 2016/2017/2018
  • Student Research Contest Program Committee at ICCAD 2018
  • Student Research Forum at IEEE/ACM ASP-DAC 2019
  • IEEE International Symposium on Intelligent Signal Processing and Communication Systems 2017

Award Review Panel

  • National Science Foundation Review Panel, 2016/2019/2020
  • Army Research Office Research Fund/Award Review Panel, 2018
  • Defense Threat Reduction Agency Review Panel, 2016
  • Ralph E. Powe Junior Faculty Award of Oak Ridge Associated Universities Review Panel, 2016
  • Hong Kong Research Grant Council, 2018/2019/2020
  • Dutch Research Council (NWO) Award Review, 2020
  • Research Grants Council of Hong Kong, 2018
  • Best paper select committee of GLSVLSI 2017
  • Best Paper select committee of ASP DAC 2018

Conference Service

  • Financial Chair, IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2019
  • Technical Area Chair, ACM Great Lakes Symposium on VLSI (GLSVLSI) 2019/2020
  • Technical Area Chair, The 20th International Symposium on Quality Electronic Design (ISQED) 2019/2020
  • Local Arrangement Chair, IEEE CyberSciTech/DASC/PICom/DataCom, Orlando, FL, 2017
  • Session Chair, IEEE International Conference On Computer Aided Design (ICCAD), San Diego, CA, 2018
  • Session Chair, IEEE International Conference on Computer Design (ICCD), Orlando, FL, 2018
  • Session ChairIEEE Computer Society Annual Symposium on VLSI (ISVLSI), HongKong, 2018
  • Session Chair, Design Automation Conference, Austin (DAC), Austin, TX, 2017/2018
  • Session Chair, Asia and South Pacific Design Automation Conference (ASP DAC), Jeju Island, Korea, 2018
  • Session Chair, IEEE International Conference on Computer Design (ICCD), Boston, MA, 2017
  • Session Chair, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, 2017/2018
  • Session Chair, Great Lakes Symposium on VLSI (GLSVLSI), Banff, Canada, 2017
  • Panelist in Neuromorphic Computing and Deep Learning, ACM/IEEE System Level Interconnect Prediction 2017 workshop, Austin, TX, 2017
  • Panelist, ACM/IEEE System Level Interconnect Prediction 2019 workshop, Las Vegas, NV, 2019

Editors of Journals

  • Guest editor of CCF THPC Special Issue on Disruptive Computing Technologies
  • Guest editor of Frontiers in Physics

Journal Technical Reviewer

  • Reviewer of Nature Electronics
  • Reviewer of IEEE Transactions on Neural Networks and Learning Systems
  • Reviewer of IEEE Transactions on Very Large Scale Integrated Systems
  • Reviewer of IEEE Transactions on Nanotechnology
  • Reviewer of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • Reviewer of IEEE Transactions on Computers
  • Reviewer of IEEE Transactions on Emerging Topics in Computing
  • Reviewer of IEEE Transactions on Emerging Topics in Computational Intelligence
  • Reviewer of IEEE Transactions on Electronic Device
  • Reviewer of IEEE Transactions on Circuits and Systems I
  • Reviewer of IEEE Transactions on Multi-Scale Computing Systems
  • Reviewer of IEEE Transactions on Circuits and Systems for Video Technology
  • Reviewer of IEEE Electron Device Letters
  • Reviewer of IEEE Magnetics Letters
  • Reviewer of IEEE Journal on Emerging and Selected Topics in Circuits and Systems
  • Reviewer of IEEE Design & Test
  • Reviewer of IEEE Journal of Exploratory Solid-State Computational Devices and Circuits
  • Reviewer of IEEE Embedded Systems Letters
  • Reviewer of IEEE Access
  • Reviewer of ACM Journal on Emerging Technologies in Computing Systems
  • Reviewer of IET Cyber-Physical Systems: Theory & Applications
  • Reviewer of Journal of Applied Physics
  • Reviewers of Royal Society of Chemistry, Nanoscale
  • Reviewers of Applied Sciences
  • Reviewer of ELSEVIER Nano Communication Networks
  • Reviewer of ELSEVIER Neurocomputing
  • Reviewer of ELSEVIER Engineering Science and Technology
  • Reviewer of ELSEVIER Integration, The VLSI Journal
  • Reviewer of ELSEVIER Physics Letters A
  • Reviewer of Journal of Computational Electronics
  • Reviewer of Journal of Systems Architecture
  • Reviewer of Electronics (ISSN 2079-9292)
  • Reviewer of AEU-International Journal of Electronics and Communications
  • Reviewer of Sensors(ISSN 1424-8220)
Professional Associations: 
  • Member of Institute of Electrical and Electronics Engineers (IEEE)
  • Member of Association for Computing Machinery (ACM)
  • Member of ACM Special Interest Group in Design Automation (SIGDA)