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Shail Dave

SW4, Instructional Aide
Student Worker, TEMPE Campus, Mailcode 8809
Student Information:
Graduate Student
Computer Engineering (Computer Systems)
Ira A Fulton Engineering


I am a graduate student in Computer Engineering at SCIDSE, ASU beginning spring 2017. Prior joining the doctoral program, I earned my master's at ASU in Computer Engineering in 2016. My coursework and interest lie in VLSI and Architecture area. In specific, I am interested in exploring compilers and architectures for accelerators. My current thesis targets researching Coarse-Grained Reconfigurable Arrays (CGRAs) which are energy-efficient accelerators that can speed-up even non-vectorizable performance-critical loops. My research at Compiler Microarchitecture Lab is guided by Prof. Aviral Shrivastava and it targets automated acceleration of general-purpose applications through CGRAs. To boost CGRA research, there is a strong need of an efficient and common platform where accelerations of various applications can be verified. Taking on this challenge, I am developing an open-source CPU-CGRA compiler-simulator infrastructure. This enables the acceleration of compute-intensive applications featuring performance-critical yet non-vectorizable loops! Simultaneously, I strive to determine better architectural choices through my work e.g. data memory bottleneck, an efficient communication interface between multi-cores and accelerator etc. My past industry experiences are in the field of RTL Design and Verification for ASIC/FPGA and I possess strong coursework in these areas. 

Research Interests

I am interested in exploring computer architectures and challenges in digital design. In particular, my research interests include, but not limited to -

  • Hardware Accelerators including Coarse-Grained Re-configurable Arrays (CGRAs)
  • Compilers
  • Embedded Systems
  • High-Performance Computing (HPC)
Research Group
  • Shail Dave, Mahesh Balasubramanian, Aviral Shrivastava, "URECA: A Compiler Solution to Manage Unified Register File for CGRAs", in Proceedings of the International Conference on Design Automation and Test in Europe (DATE), 2018
  • Mahesh Balasubramanian, Shail Dave, Aviral Shrivastava, Reiley Jeyapaul, "LASER: A Hardware/Software Approach to Accelerate Complicated Loops on CGRAs",  in Proceedings of the International Conference on Design Automation and Test in Europe (DATE), 2018
  • Scalable Register File Architecture for CGRA Accelerators, Master's Thesis, SCIDSE, ASU
Research Activity

Poster Presentations:

  • Shail Dave, "CGRAs for Accelerated Power-Efficient Computing"53rd Annual Design Automation Conference (DAC), 2016 (Richard A. Newton Young Fellow Presentations)
Fall 2017
Course NumberCourse Title
CSE 420Computer Architecture I
Honors / Awards

A. Richard Newton Young Student Fellowship - 53rd Design Automation Conference
GPSA Travel Grant Arizona State University, Summer 2016

Professional Associations
  • IEEE Computer Society
  • IEEE Student Membership
  • IEEE Council on Design Automation (CEDA)
  • Eta Kappa Nu

External/Expert Reviewer -

  • ACM Transactions on Embedded Computing Systems (TECS) - 2017
  • IEEE Transactions on Multi-Scale Computing Systems (TMSCS) - 2016, 2017
  • ACM Design Automation Conference - 2018
  • IEEE/ACM/IFIP International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS) - 2016, 2017
  • International Conference on Design Automation and Test in Europe (DATE) - 2016, 2017
  • International Conference on VLSI Design (VLSID) - 2017, 2018
  • International Journal on Design Automation for Embedded Systems, Springer - 2017

Graduate Vice Chair, IEEE Eta Kappa Nu, ASU Chapter (2016-2017)

Industry Positions
  • ASIC Verification Engineer Intern, SanDisk Corporation, Milpitas, CA (Summer 2015) 
  • Intern, Space Application Center, Indian Space Research Organization, India (Spring 2014)