I am a graduate student in Computer Engineering at SCIDSE, ASU beginning spring 2017. Prior joining the doctoral program, I earned my master's at ASU in Computer Engineering in 2016. My coursework and interest lie in VLSI and Architecture area. In specific, I am interested in exploring compilers and architectures for accelerators. My current thesis targets researching Coarse-Grained Reconfigurable Arrays (CGRAs) which are energy-efficient accelerators that can speed-up even non-vectorizable performance-critical loops. My research at Compiler Microarchitecture Lab is guided by Prof. Aviral Shrivastava and it targets automated acceleration of general-purpose applications through CGRAs. To boost CGRA research, there is a strong need of an efficient and common platform where accelerations of various applications can be verified. Taking on this challenge, I am developing an open-source CPU-CGRA compiler-simulator infrastructure. This enables the acceleration of compute-intensive applications featuring performance-critical yet non-vectorizable loops! Simultaneously, I strive to determine better architectural choices through my work e.g. data memory bottleneck, an efficient communication interface between multi-cores and accelerator etc. My industry experiences are in the field of compilers, RTL Design/Verification for ASIC/FPGA.
I am interested in exploring computer architectures and challenges in digital design. In particular, my research interests include, but not limited to -
Compiler Microarchitecture Lab
SCIDSE, ASU, Tempe
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