I am a PhD student (majoring in Computer Engineering) at Arizona State University. My research interests lie in exploring challenges dealing with computing systems (in particular, about developing compiler and architecture design and optimizations for programmable accelerators). My research at Compiler Microarchitecture Lab is advised by Prof. Aviral Shrivastava, focusing on "Coarse-Grained Reconfigurable Accelerators (CGRAs) for Domain-customized and General-purpose Computing". CGRAs are popular energy-efficient dataflow accelerators that can efficiently speed-up performance-critical loops of imaging and media processing applications, machine learning, embedded systems, and even non-vectorizable loop kernels. My prior industry experiences include compiler optimizations and code generation for embedded systems, as well as RTL design and verification for ASIC and FPGA platforms.
My interest lies in exploring challenges dealing with computing systems (in particular, about developing compiler solution and architecture design for programmable dataflow accelerators).
Coarse-grained reconfigurable dataflow accelerators (CGRAs) are shown as very effective for domain-specific accelerations, including for machine learning, high-performance and scientific computing, and graph processing applications. They comprise of an array of processing elements with private register files and a shared scratchpad memory. CGRAs are promising because they feature simplicity, programmability, and energy-efficiency.
Automatic and efficient accelerations of machine learning models on dataflow accelerators is challenging, particularly due to varying sizes of model layers and tensor dimensions. Vast space of execution methods make mapping optimizations even more challenging. Besides accelerating dense tensor computations at their maximum, accelerating compressed models can provide further significant acceleration opportunities. So, I am recently investigating the throughput and energy-efficiency benefits in accelerating such applications through dataflow accelerators as well as optimizing the dataflow execution for the same. My research goal lies in determining the optimized architecture and compiler solutions and to establish a complete system-stack with which, machine learning models from TensorFlow-like libraries can be executed on coarse-grained dataflow accelerators. In our early efforts, we have recently developed dMazeRunner framework which obtains (within seconds) efficient mappings that are non-intuitive and flexibly adapts to the characteristics of the loop-kernels and target accelerator architectures. It also allows non-expert designers or developers to explore acceleration opportunities of DNNs on CGRAs through HW-SW co-designs.
My research interests include:
Compiler Microarchitecture Lab
School of Computing, Informatics, Decisions and Systems Engineering (CIDSE),
Ira A. Fulton Schools of Engineering,
Arizona State University, Tempe, AZ.
Other lectures/recitations during Teaching Assistantship (Fall 2016 – Spring 2018)
Travel Grant Awards from:
External and/or Expert Reviewer:
Recent Voluntary Activities: