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Shail Dave

Sch Compt Infor & Dec Sys Engr
Grad Research Associate
Graduate Assistant/Associate, TEMPE Campus, Mailcode 8809
Student Information:
Graduate Student
Computer Engineering (Computer Systems)
Ira A Fulton Engineering


I am a PhD student (majoring in Computer Engineering) at Arizona State University. My research interests lie in exploring challenges dealing with computing systems (in particular, about developing compiler and architecture design and optimizations for programmable accelerators). My research at Compiler Microarchitecture Lab is advised by Prof. Aviral Shrivastava, focusing on "Coarse-Grained Reconfigurable Accelerators (CGRAs) for Domain-customized and General-purpose Computing". CGRAs are popular energy-efficient dataflow accelerators that can efficiently speed-up performance-critical loops of imaging and media processing applications, machine learning, embedded systems, and even non-vectorizable loop kernels. My prior industry experiences include compiler optimizations and code generation for embedded systems, as well as RTL design and verification for ASIC and FPGA platforms. 

  • M.S., Computer Engineering, Arizona State University, 2016
  • B.E., Electronics and Communication Engineering, L. D. College of Engineering, Ahmedabad 2014 
Research Interests: 

My interest lies in exploring challenges dealing with computing systems (in particular, about developing compiler solution and architecture design for programmable dataflow accelerators).

Coarse-grained reconfigurable dataflow accelerators (CGRAs) are shown as very effective for domain-specific accelerations, including for machine learning, high-performance and scientific computing, and graph processing applications. They comprise of an array of processing elements with private register files and a shared scratchpad memory. CGRAs are promising because they feature simplicity, programmability, and energy-efficiency. 

Automatic and efficient accelerations of machine learning models on dataflow accelerators is challenging, particularly due to varying sizes of model layers and tensor dimensions. Vast space of execution methods make mapping optimizations even more challenging. Besides accelerating dense tensor computations at their maximum, accelerating compressed models can provide further significant acceleration opportunities. So, I am recently investigating the throughput and energy-efficiency benefits in accelerating such applications through dataflow accelerators as well as optimizing the dataflow execution for the same. My research goal lies in determining the optimized architecture and compiler solutions and to establish a complete system-stack with which, machine learning models from TensorFlow-like libraries can be executed on coarse-grained dataflow accelerators. In our early efforts, we have recently developed dMazeRunner framework which obtains (within seconds) efficient mappings that are non-intuitive and flexibly adapts to the characteristics of the loop-kernels and target accelerator architectures. It also allows non-expert designers or developers to explore acceleration opportunities of DNNs on CGRAs through HW-SW co-designs.

My research interests include:

  • Hardware Accelerators
  • Deep Learning
  • Computer Architecture
  • Compiler Design and Optimizations
  • Embedded Systems
  • Hardware/Software Co-Design
  • High-Performance Computing
  • Shail Dave, Youngbin Kim, Sasikanth Avancha, Kyoungwoo Lee, Aviral Shrivastava, "dMazeRunner: Optimizing Convolutions on Dataflow Accelerators", in 45th International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2020).
  • Shail Dave, Youngbin Kim, Sasikanth Avancha, Kyoungwoo Lee, Aviral Shrivastava, "dMazeRunner: Executing Perfectly Nested Loops on Dataflow Accelerators", in ACM Transactions on Embedded Computing Systems (TECS) [Special Issue on ESWEEK 2019 - ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)]  [Paper] [Code
  • Shail Dave, Mahesh Balasubramanian, and Aviral Shrivastava. "RAMP: resource-aware mapping for CGRAs." In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), pp. 1-6. IEEE, 2018. [Paper] [Slides] [Poster]
  • Shail Dave, Mahesh Balasubramanian, and Aviral Shrivastava. "URECA: A Compiler Solution to Manage Unified Register File for CGRAs." In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, pp. 1081-1086. IEEE, 2018. [Paper] [Slides]
  • Mahesh Balasubramanian, Shail Dave, Aviral Shrivastava, and Reiley Jeyapaul. "LASER: A hardware/software approach to accelerate complicated loops on CGRAs." In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, pp. 1069-1074. IEEE, 2018. [Paper] [Slides]
Fall 2017
Course NumberCourse Title
CSE 420Computer Architecture I

Invited Lectures/Talks

  • Guest Lecture on " Energy-efficient Acceleration of Residual Neural Nets onto Dataflow Accelerators", CSE 420: Computer Architecture I, Fall 2018  [class size: 115]
  • Guest Lecture on "Dataflow Accelerators", ASU 101: The ASU Experience, Fall 2018 [class size: 19]
  • Invited Talk on "Exploring Career Opportunities and Skill Enhancement" at sessions in International Student Orientation, ASU, Fall 2016 [total attendees: about 250]
  • Invited Talk and Panel Discussion on "Leadership and Involvement Opportunities and Skill Enhancement", organized by Graduate and Professional Students Association (GPSA) during International Student Orientation, Spring 2016 [attendees: about 20]

Other lectures/recitations during Teaching Assistantship (Fall 2016 – Spring 2018)

  • CSE 100: Principles of Programming with C++
  • CSE 330: Operating Systems
  • CSE 420: Computer Architecture  (Outstanding TA Award) 
Honors / Awards: 
  • Engineering Grad Fellowship, Ira A. Fulton Schools of Engineering, ASU – 2018, 2019, 2020
  • Doctoral Fellowship, School of Computing, Informatics, Decisions and Systems Engineering (CIDSE), Spring 2019
  • A. Richard Newton Young Student Fellowship – 53rd Annual Design Automation Conference (DAC), June 2016
  • Outstanding Computer Engineering TA Award, School of Computing, Informatics, Decisions and Systems Engineering (CIDSE), ASU – Spring 2018
  • Student lead, ASU team, for project funded by NSF/Intel joint research center for Computer Assisted Programming for Heterogeneous Architectures (CAPA).

Travel Grant Awards from:

  • School of Computing, Informatics, Decisions and Systems Engineering (CIDSE), ASU – 2018, 2019
  • Computer Engineering, ASU – Spring 2018
  • Graduate and Professional Student Association (GPSA), ASU – Summer 2016, Spring 2018, Fall 2019
  • Graduate College, ASU – 2019
  • ACM SIGDA and SIGBED – 2018, 2019
Professional Associations: 

Student Membership:

  • Association for Computing Machinary (ACM)
  • ACM Special Interest Group on Computer Architecture (SIGARCH)
  • ACM Special Interest Group on Embedded Systems (SIGBED)
  • Institute of Electrical and Electronics Engineers (IEEE)
  • IEEE Computer Society
  • IEEE Council on Design Automation (CEDA)
  • IEEE Computer Society Technical Committee on Computer Architecture (TCCA)
  • Eta Kappa Nu

External and/or Expert Reviewer:

  • ACM Design Automation Conference (DAC) – 2018, 2019, 2020
  • IEEE International Conference on Design Automation and Test in Europe (DATE) – 2016, 2017
  • IEEE/ACM/IFIP International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS) – 2016, 2017
  • International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) – 2019
  • IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) – 2019
  • IEEE International Conference on Computer Design (ICCD) – 2019
  • International Conference on VLSI Design and Embedded Systems (VLSID & ES) – 2017, 2018

Journals Referring: 

  • ACM Transactions on Embedded Computing Systems (TECS) – 2017, 2019, 2020
  • IEEE Transactions on Multi-Scale Computing Systems (TMSCS) – 2016, 2017
  • International Journal on Design Automation for Embedded Systems, Springer – 2017

Recent Voluntary Activities:

  • Graduate Vice Chair, IEEE Eta Kappa Nu, ASU Chapter (2016–2017)
  • Invited Speaker, International Student Orientation, ASU – 2016, 2017 
  • Webmaster, Compiler Microarchitecture Lab, 2017–Present
  • Invited Panelist on Early Career Panel, ASU 101: The ASU Experience, Fall 2018
Industry Positions: 
  • Software Engineer (Intern), The Mathworks, Natick, MA (May 2018–Aug 2018)
    Research Group: Code Efficiency, Embedded Coder
    Project: Loop Optimizations for Target-Aware Code Generation
  • ASIC Verification Engineer Intern, SanDisk Corporation, Milpitas, CA (Summer 2015) 
    Project: Module-level verification of enterprise solid state drive controller ASIC
  • Intern, Space Application Center, Indian Space Research Organization, India (Spring 2014)
    Project: End-to-end System Development for Precise Temperature Control of Cryogenic Cooler Systems