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Shail Dave

Sch Compt Infor & Dec Sys Engr
Grad Research Associate
Graduate Assistant/Associate, TEMPE Campus, Mailcode 8809
Student Information:
Graduate Student
Computer Engineering (Computer Systems)
Ira A Fulton Engineering


I am a PhD student (majoring in Computer Engineering) at Arizona State University. My interest lies in exploring challenges dealing with computing systems (in particular, about developing compiler solution and architecture design for programmable dataflow accelerators). My research at Compiler Microarchitecture Lab is advised by Prof. Aviral Shrivastava and it includes enabling automated acceleration of the workloads onto Coarse-Grained Reconfigurable Arrays (CGRAs). CGRAs are energy-efficient dataflow accelerators that can efficiently speed-up even non-vectorizable performance-critical loops. My prior industry experiences include compiler optimizations and code generation for embedded systems, and RTL design and verification for ASIC and FPGA platforms. 

  • M.S., Computer Engineering, Arizona State University, 2016
  • B.E., Electronics and Communication Engineering, L. D. College of Engineering, Ahmedabad 2014 
Research Interests

My interest lies in exploring challenges dealing with computing systems (in particular, about developing compiler solution and architecture design for programmable dataflow accelerators).

Dataflow accelerators including Coarse-Grained Reconfigurable Arrays (CGRAs), CGRA-like spatial architectures (e.g. Eyeriss system from MIT) or, systolic array based accelerators (e.g. Tensor Processing Unit) are recently being developed and analyzed by the industry and academia. Owing to their significantly high energy-efficiency, the dataflow accelerators are demonstrated as a very promising solution to accelerate compute- and memory-intense applications e.g. deep neural networks (DNN). So, I am recently investigating the throughput and energy-efficiency benefits in accelerating such applications through dataflow accelerators as well as optimizing the dataflow execution for the same. The research goal is to determine the optimized architecture and compiler solutions and to establish a complete system-stack with which, DNN models from TensorFlow-like libraries can be executed on CGRA-like dataflow accelerators.

Moreover, my research interests include:

  • Hardware Accelerators including Coarse-Grained Re-configurable Arrays (CGRAs)
  • Deep Learning
  • Compilers
  • Embedded Systems
  • High-Performance Computing
Research Group
  • Dave, Shail, Mahesh Balasubramanian, and Aviral Shrivastava. "RAMP: resource-aware mapping for CGRAs." In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), pp. 1-6. IEEE, 2018.
  • Dave, Shail, Mahesh Balasubramanian, and Aviral Shrivastava. "URECA: A Compiler Solution to Manage Unified Register File for CGRAs." In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, pp. 1081-1086. IEEE, 2018.
  • Balasubramanian, Mahesh, Shail Dave, Aviral Shrivastava, and Reiley Jeyapaul. "LASER: A hardware/software approach to accelerate complicated loops on CGRAs." In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, pp. 1069-1074. IEEE, 2018.
Fall 2017
Course NumberCourse Title
CSE 420Computer Architecture I
  • Guest Lecture on " Energy-efficient Acceleration of Residual Neural Nets onto Dataflow Accelerators", CSE 420: Computer Architecture I, Fall 2018  [class size: 115]
  • Guest Lecture on "Dataflow Accelerators", ASU 101: The ASU Experience, Fall 2018 [class size: 19]
  • Invited Talk on "Exploring Career Opportunities and Skill Enhancement" at sessions in International Student Orientation, ASU, Fall 2016 [total attendees: about 250]
  • Invited Talk and Panel Discussion on "Leadership and Involvement Opportunities and Skill Enhancement", organized by Graduate and Professional Students Association (GPSA) during International Student Orientation, Spring 2016 [attendees: about 20]
Honors / Awards
  • Outstanding CEN TA Award, CIDSE, ASU – Spring 2018
  • Engineering Grad Fellowship, Arizona State University, April 2018
  • A. Richard Newton Young Student Fellowship – 53rd Annual Design Automation Conference (DAC), June 2016

Travel Grant Awards from:

  • School of Computing, Informatics, Decisions and Systems Engineering (CIDSE), ASU – Summer 2018
  • Computer Engineering, ASU – Spring 2018
  • Graduate and Professional Student Association (GPSA), ASU – Summer 2016, Spring 2018
Professional Associations

Student Membership:

  • Association for Computing Machinary (ACM)
  • ACM Special Interest Group on Computer Architecture (SIGARCH)
  • Institute of Electrical and Electronics Engineers (IEEE)
  • IEEE Computer Society
  • IEEE Council on Design Automation (CEDA)
  • IEEE Computer Society Technical Committee on Computer Architecture (TCCA)
  • Eta Kappa Nu

External/Expert Reviewer:

  • ACM Design Automation Conference (DAC) – 2018
  • IEEE/ACM/IFIP International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS) – 2016, 2017
  • International Conference on Design Automation and Test in Europe (DATE) – 2016, 2017
  • International Conference on VLSI Design and Embedded Systems (VLSID & ES) – 2017, 2018

Journals Referring: 

  • ACM Transactions on Embedded Computing Systems (TECS) – 2017
  • IEEE Transactions on Multi-Scale Computing Systems (TMSCS) – 2016, 2017
  • International Journal on Design Automation for Embedded Systems, Springer – 2017

Recent Voluntary Activities:

  • Graduate Vice Chair, IEEE Eta Kappa Nu, ASU Chapter (2016–2017)
  • Invited Speaker, International Student Orientation, ASU – 2016, 2017 
  • Webmaster, Compiler Microarchitecture Lab, 2017–Present
  • Invited Panelist on Eary Career Panel, ASU 101: The ASU Experience, Fall 2018
Industry Positions
  • Software Engineer (Intern), Code Efficiency Group, The Mathworks, Natick, MA (May 2018–Aug 2018)
  • ASIC Verification Engineer Intern, SanDisk Corporation, Milpitas, CA (Summer 2015) 
  • Intern, Space Application Center, Indian Space Research Organization, India (Spring 2014)