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Biography: 

Brian Joseph Coppa has nearly two decades of microelectronics industry experience from Micron/Intel, ASM, and Tokyo Electron; as a consultant to several other leaders in the field. He has authored over 15 US and foreign patent publications and numerous technical journal articles, which have received many prestigious citations globally. Most notably, he co-patented the 1st self-aligned double patterning (SADP) used in production for IC shrinks & developed the ultra-critical atomic layer deposited (ALD) spacer process. Brian is a Senior Member of the Institute of the Electrical and Electronics Engineer (IEEE) Society and co-chair of the SEMI Standard Americas Smart Manufacturing Council. Most recently, Brian has been a Principal Applications Engineer for EMD Performance Materials, a branch of Merck KGaA, focused on leading-edge semiconductor chemical & gas delivery solutions. He is a Visiting Faculty/Scholar at ASU in the Department of Electrical, Computer and Energy Engineering.

Education: 

Ph.D. and Master's - Materials Science and Engineering at North Carolina State University 

B.S. - Physics at University of Arizona

Industry Positions: 

Micron- Process Development and Device Integration Engineer

ASM- Senior Process Development Engineer

Tokyo Electron- Senior Process Engineering Lead

Merck KGaA/EMD Performance Materials- Principal Applications Engineer

Senior Consultant- numerous miscellaneous companies across microelectronics supply chain