Brian Joseph Coppa has nearly two decades of microelectronics industry experience from Micron/Intel, ASM, Tokyo Electron and Merck/EMD Electronics; as a consultant to numerous other companies across the supply chain. He has authored over 15 US and foreign patent publications and numerous technical journal articles, which have received many prestigious citations globally. Most notably, he co-patented the 1st self-aligned double patterning (SADP) used in production for IC shrinks that became core to the industry roadmap & developed the key enabling atomic layer deposited (ALD) spacer process. Brian is a Senior Member of the Institute of the Electrical and Electronics Engineer (IEEE) Society and co-chair of the SEMI Standard Americas Smart Manufacturing Council. Currently, Brian is a Business Development Engineering Lead with Ulvac Technologies Inc. focused on the microelectronics/IC process equipment and vacuum systems market. He is a Visiting Faculty Scholar at ASU in the Department of Electrical, Computer and Energy Engineering.
Ph.D. and Master's - Materials Science and Engineering at North Carolina State University
B.S. - Physics at University of Arizona
Micron- Process Development and Device Integration Engineer
ASM- Senior Process Development Engineer
Tokyo Electron- Senior Process Engineering Lead
Merck KGaA/EMD Performance Materials- Principal Applications Engineer
Senior Consultant- numerous miscellaneous companies across microelectronics supply chain